How to predict DMA latencies

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Where:

•

Where:

3.1.2

DMA transfer time versus concurrent access

Additional latency can be added to the DMA service timing described in Section 3.1.1 when

several masters try to access simultaneously to the same slave.

For peripheral and memory worst-case access/transfer time, the following factors impact the

total delay time for DMA stream service:

•

When several masters are accessing the same AHB destination simultaneously, the

DMA latency is impacted; the DMA transfer cannot start until the bus matrix arbiter

grants access to the DMA as described in Section 2.1.2.

•

When several masters (DMA and CPU) are accessing the same AHB-to-APB bridge,

the DMA transfer time is delayed due to the AHB-to-APB bridge arbitration as

described in Section 2.3.2.

Table 7. Peripheral port access/transfer time versus DMA path used

Description

Through bus matrix

DMA’s

direct paths

To AHB

peripherals

To APB

peripherals

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

N/A

2. For FMC, an additional cycle can be added depending on the external memory used. Additional AHB

cycles are added depending on external memory timings.

2 APB cycles

2 APB cycle

N/A

1 AHB cycle

1 AHB cycle

Table 8. Memory port access/transfer time

Description

Latency

1 AHB cycle

1 AHB cycle

2. For consecutive SRAM accesses (while no other master accesses the same SRAM in-between),

1 AHB cycle