LAN9500AI datasheet(105/213 Pages) MICROCHIP

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DS00001875A-page 105

LAN950x

5.12.1.3

Remote Wake Generation

5.12.1.3.1

Wake On LAN Event or Energy DetecT

bit Control bits (Note 5-6) are implemented in the MAC’s Wakeup Control and Status Register (WUCSR) to control

Global Unicast Frame Wakeup, Magic Packet Wakeup, Wake Up Frame Detection Wakeup, Perfect DA Frame Wakeup,

and Broadcast Frame Wakeup: GUEN, MPEN, WUEN, PFDA_EN, and BCAST_EN, respectively. A composite signal,

depending on the state of these control bits and the associated event, is generated and propagated for further process-

ing, as discussed in the following text.

Note 5-6

(LAN9500A/LAN9500Ai ONLY):

The five specified control bits are supported.

(LAN9500/LAN9500i ONLY):

Only three control bits are supported - GUEN, MPEN, WUEN.

Two control bits are implemented in the PMT_CTRL SCSR: Wake-on-LAN enable (WOL_EN) and Energy Detect enable

(ED_EN). Depending on the state of these control bits, the logic will generate an internal wake event interrupt when the

MAC detects a wakeup event (Global Unicast Frame, Wakeup Frame, Magic Packet, Perfect Destination Address

Frame (Note 5-7), or Broadcast Frame (Note 5-7) - depending on the state of the aforementioned composite signal), or

a PHY interrupt is asserted (energy detect). Two Wakeup Status (WUPS) bits are implemented in the SCSR space.

These bits are set depending on the corresponding wake event. (See Section 7.3.8, "Power Management Control Reg-

ister (PMT_CTL)," on page 127 for further information). If a Wake-on-LAN event is detected, then further resolution on

the source of the event can be obtained by examining the Remote Wakeup Frame Received (WUFR), Magic Packet

Received (MPR), Perfect DA Frame Received (PFDA_FR) (Note 5-7), and Broadcast Frame Received (BCAST_FR)

(Note 5-7) status bits in the MAC’s Wakeup Control and Status Register (WUCSR).

Note:

The IME bit is in the Hardware Configuration Register (HW_CFG). General Purpose IO Configuration Reg-

ister (GPIO_CFG) and General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE) must be set

accordingly. PHY Link Up Enable (PHY_LINKUP_EN) bit of the General Purpose IO Wake Enable and

Polarity Register (GPIO_WAKE) must be set if PHY Link Up is to cause wake event. Diagram does not

represent actual hardware implementation.

FIGURE 5-36:

DETAILED GPIOS 8-10 WAKE DETECTION LOGIC (LAN9500A/LAN9500AI)

Note:

The IME bit is in the Hardware Configuration Register (HW_CFG). LED General Purpose IO Configuration

must be set accordingly. Diagram does not represent actual hardware implementation.

GPIOn_INT clear

GPIOn

GPIOPOLn

Latch

GPDIRn

GPDn

GPCTLn[0]

GPIOWKn

GPIOn_DET

IME

GPCTLn[1]

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