| 전자부품 데이터시트 검색엔진 |
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C161PI 데이터시트(PDF) 77 Page - Infineon Technologies AG |
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C161PI 데이터시트(HTML) 77 Page - Infineon Technologies AG |
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77 / 82 page ![]() &3, Data Sheet 75 1999-07 AC Characteristics CLKOUT and READY (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1 / 2TCL = 1 to 20 MHz Unit min. max. min. max. CLKOUT cycle time W 29 CC 40 40 2TCL 2TCL ns CLKOUT high time W 30 CC 15 – TCL – 10 – ns CLKOUT low time W 31 CC 13 – TCL – 12 – ns CLKOUT rise time W 32 CC – 12 – 12 ns CLKOUT fall time W 33 CC – 8 –8ns CLKOUT rising edge to ALE falling edge W 34 CC 0 + W A 8 + W A 0 + W A 8 + W A ns Synchronous READY setup time to CLKOUT W 35 SR 18 – 18 – ns Synchronous READY hold time after CLKOUT W 36 SR 4 – 4–ns Asynchronous READY low time W 37 SR 68 – 2TCL + W 58 –ns Asynchronous READY setup time 1) 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. W 58 SR 18 – 18 – ns Asynchronous READY hold time 1) W 59 SR 4 – 4–ns Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2 W A and WC refer to the next following bus cycle, WF refers to the current bus cycle. The maximum limit for W 60 must be fulfilled if the next following bus cycle is READY controlled. W 60 SR 0 0 + 2 W A + W C + WF 2) 0 TCL - 25 + 2 W A + WC + W F 2) ns |
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