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PI7C8150BMA-33 데이터시트(PDF) 33 Page - Pericom Semiconductor Corporation

부품명 PI7C8150BMA-33
상세설명  ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PDF  107 Pages
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제조업체  PERICOM [Pericom Semiconductor Corporation]
홈페이지  http://www.pericom.com
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PI7C8150BMA-33 데이터시트(HTML) 33 Page - Pericom Semiconductor Corporation

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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Page 33 of 107
April 2015 – Revision 2.1
to Type 1 forwarding occurs when the following conditions are met during the address
phase:
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
The bus command is a configuration read or write transaction.
PI7C8150B also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to support upstream special cycle generation. A Type 1 configuration command
is forwarded upstream when the following conditions
are met:
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
The PI7C8150B forwards Type 1 to Type 1 configuration write transactions as delayed
transactions. Type 1 to Type 1 configuration write transactions are limited to a single data
transfer.
3.7.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in
hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and
are not forwarded across the bridge. Special cycle transactions can be generated from Type
1 configuration write transactions in either the upstream or the down-stream direction.
PI7C8150B initiates a special cycle on the target bus when a Type 1 configuration write
transaction is being detected on the initiating bus and the following conditions are met
during the address phase:
The lowest two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in
configuration space for downstream forwarding or equal to the value in the primary
bus number register in configuration space for upstream forwarding.
15-0048



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