PI7C8150BMA-33 datasheet(22/107 Pages) PERICOM

22 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 22 of 107

April 2015 – Revision 2.1

PCI BUS OPERATION

This Chapter offers information about PCI transactions, transaction forwarding across

PI7C8150B, and transaction termination. The PI7C8150B has two 128-byte FIFO’s for

buffering of upstream and downstream transactions. These hold addresses, data,

commands, and byte enables that are used for write transactions. The PI7C8150B also has

an additional four 128-byte FIFO’s that hold addresses, data, commands, and byte enables

for read transactions.

3.1

TYPES OF TRANSACTIONS

This section provides a summary of PCI transactions performed by PI7C8150B.

Table 3-1 lists the command code and name of each PCI transaction. The Master and

Target columns indicate support for each transaction when PI7C8150B initiates

transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B

responds to transactions as a target, on the primary (P) and secondary (S) buses.

Table 3-1. PCI Transactions

Types of Transactions

Initiates as Master

Responds as Target

Primary

Secondary

Primary

Secondary

0000

Interrupt Acknowledge

0001

Special Cycle

0010

I/O Read

0011

I/O Write

0100

Reserved

0101

Reserved

0110

Memory Read

0111

Memory Write

1000

Reserved

1001

Reserved

1010

Configuration Read

1011

Configuration Write

Y (Type 1 only)

1100

Memory Read Multiple

1101

Dual Address Cycle

1110

Memory Read Line

1111

Memory Write and Invalidate

As indicated in Table 3-1, the following PCI commands are not supported by PI7C8150B:



PI7C8150B never initiates a PCI transaction with a reserved command code and, as a

target, PI7C8150B ignores reserved command codes.



PI7C8150B does not generate interrupt acknowledge transactions. PI7C8150B

ignores interrupt acknowledge transactions as a target.



PI7C8150B does not respond to special cycle transactions. PI7C8150B cannot

guarantee delivery of a special cycle transaction to downstream buses because of the

broadcast nature of the special cycle command and the inability to control the

transaction as a target. To generate special cycle transactions on other PCI buses,

either upstream or downstream, Type 1 configuration write must be used.



PI7C8150B neither generates Type 0 configuration transactions on the primary PCI

bus nor responds to Type 0 configuration transactions on the secondary PCI buses.

15-0048

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