PI7C8150BMA-33 datasheet(55/107 Pages) PERICOM

55 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 55 of 107

April 2015 – Revision 2.1



PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the parity error

response bit is set in the bridge control register of the secondary interface.



PI7C8150B sets the parity error detected bit in the status register of the secondary

interface.



PI7C8150B captures and forwards the bad parity condition to the primary bus.



PI7C8150B completes the transaction normally.

During downstream write transactions, when a data parity error is reported on the target

(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:



PI7C8150B sets the data parity detected bit in the status register of secondary interface,

if the parity error response bit is set in the bridge control register of the secondary

interface.



PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status



The SERR_L enable bit is set in the command register.



The posted write parity error bit of P_SERR_L event disable register is not

set.



The parity error response bit is set in the bridge control register of the

secondary interface.



The parity error response bit is set in the command register of the primary

interface.



PI7C8150B has not detected the parity error on the primary (initiator) bus

which the parity error is not forwarded from the primary bus to the

secondary bus.

During upstream write transactions, when a data parity error is reported on the target

(primary) bus by the target’s assertion of P_PERR_L, the following events occur:



PI7C8150B sets the data parity detected bit in the status register, if the parity error

response bit is set in the command register of the primary interface.



PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status



The SERR_L enable bit is set in the command register.



The parity error response bit is set in the bridge control register of the

secondary interface.



The parity error response bit is set in the command register of the primary

interface.



PI7C8150B has not detected the parity error on the secondary (initiator) bus,

which the parity error is not forwarded from the secondary bus to the

primary bus.

15-0048

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