PI7C8150BMA-33 datasheet(72/107 Pages) PERICOM

72 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 72 of 107

April 2015 – Revision 2.1

When the chip reset bit is set, all registers and chip state are reset and all signals are

tristated. S_RESET_L is asserted and the secondary reset bit is automatically set.

S_RESET_L remains asserted until a configuration write operation clears the secondary

reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after

completion of the configuration write operation, PI7C8150B’s reset bit automatically clears

and PI7C8150B is ready for configuration.

During reset, PI7C8150B is inaccessible.

SUPPORTED COMMANDS

The PCI command set is given below for the primary and secondary interfaces.

13.1

PRIMARY INTERFACE

P_CBE [3:0]

Command

Action

0000

Interrupt

Acknowledge

Ignore

0001

Special Cycle

Do not claim. Ignore.

0010

I/O Read

1. If address is within pass through I/O range, claim and pass

through.

2. Otherwise, do not pass through and do not claim for

internal access.

0011

I/O Write

Same as I/O Read.

0100

Reserved

-----

0101

Reserved

-----

0110

Memory Read

1. If address is within pass through memory range, claim and

pass through.

2. If address is within pass through memory mapped I/O

range, claim and pass through.

3. Otherwise, do not pass through and do not claim for

internal access.

0111

Memory Write

Same as Memory Read.

1000

Reserved

-----

1001

Reserved

-----

1010

Configuration Read

Type 0 Configuration Read:

If the bridge’s IDSEL line is asserted, perform function

decode and claim if target function is implemented.

Otherwise, ignore. If claimed, permit access to target

function’s configuration registers. Do not pass through

under any circumstances.

Type 1 Configuration Read:

1. If the target bus is the bridge’s secondary bus: claim and

pass through as a Type 0 Configuration Read.

2. If the target bus is a subordinate bus that exists behind the

bridge (but not equal to the secondary bus): claim and pass

through as a Type 1 Configuration Read.

3. Otherwise, ignore.

1011

Configuration Write

Type 0 Configuration Write: same as Configuration

Read.

Type 1 Configuration Write (not special cycle request):

1. If the target bus is the bridge’s secondary bus: claim and

pass through as a Type 0 Configuration Write

2. If the target bus is a subordinate bus that exists behind the

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