PI7C8150BMA-33 datasheet(38/107 Pages) PERICOM

38 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 38 of 107

April 2015 – Revision 2.1



PI7C8150B receives a target abort.

PI7C8150B makes 2

24 (default) read attempts resulting in a response of target retry.

Table 3-9. Response to Delayed Read Target Termination

Target Termination

Response

Normal

If prefetchable, target disconnect only if initiator requests more data than read

from target. If non-prefetchable, target disconnect on first data phase.

Target Retry

Re-initiate read transaction to target

Target Disconnect

If initiator requests more data than read from target, return target disconnect to

initiator.

Target Abort

Return target abort to initiator. Set received target abort bit in the target

interface status register. Set signaled target abort bit in the initiator interface

status register.

After PI7C8150B makes 2

24(default) attempts of the same delayed read transaction on the

target bus, PI7C8150B asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of

command register for secondary bus) and the delayed-write-non-delivery bit is not set. The

delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).

PI7C8150B will report system error. See Section 6.4 for a description of system error

conditions.

3.8.4

TARGET TERMINATION INITIATED BY PI7C8150B

PI7C8150B can return a target retry, target disconnect, or target abort to an initiator for

reasons other than detection of that condition at the target interface.

3.8.4.1

TARGET RETRY

PI7C8150B returns a target retry to the initiator when it cannot accept write data or return

read data as a result of internal conditions. PI7C8150B returns a target retry to an initiator

when any of the following conditions is met:

For delayed write transactions:



The transaction is being entered into the delayed transaction queue.



Transaction has already been entered into delayed transaction queue, but target

response has not yet been received.



Target response has been received but has not progressed to the head of the return

queue.



The delayed transaction queue is full, and the transaction cannot be queued.



A transaction with the same address and command has been queued.



A locked sequence is being propagated across PI7C8150B, and the write transaction is

not a locked transaction.



The target bus is locked and the write transaction is a locked transaction.



Use more than 16 clocks to accept this transaction.

For delayed read transactions:

15-0048

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