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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP320C2811PBKA 데이터시트(PDF) 111 Page - Texas Instruments |
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TMP320C2811PBKA 데이터시트(HTML) 111 Page - Texas Instruments |
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111 / 147 page  Electrical Specifications 111 June 2004 SPRS257 Table 6−23. SPI Slave Mode External Timing (Clock Phase = 1)†‡ NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns 13§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 13§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 14§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 14§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 17§ tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns 17§ tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S ns 18§ tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0.75tc(SPC)S ns 18§ tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0.75tc(SPC)S ns 21§ tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0 ns 21§ tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0 ns 22§ tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S ns 22§ tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S ns † The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set. ‡ tc(SPC) = SPI clock cycle time = LSPCLK 4 or LSPCLK (SPIBRR ) 1) tc(LCO) = LSPCLK cycle time § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Data Valid 22 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid 21 12 18 17 14 13 SPISTE† † In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 1) |
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