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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP320C2811PBKA 데이터시트(PDF) 113 Page - Texas Instruments |
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TMP320C2811PBKA 데이터시트(HTML) 113 Page - Texas Instruments |
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113 / 147 page  Electrical Specifications 113 June 2004 SPRS257 • If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then: 1. Lead: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 2. Active: AR ≥ 2 x tc(XTIM) AW ≥ 2 x tc(XTIM) NOTE: Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions†: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 1 ≥ 1 ≥ 0 ≥ 1 ≥ 1 ≥ 0 0, 1 † No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Synchronous XREADY†: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Invalid 1 0 0 1 0 0 0, 1 Valid 1 1 0 1 1 0 0, 1 † No hardware to detect illegal XTIMING configurations • If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then: 1. Lead: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 2. Active: AR ≥ 2 x tc(XTIM) AW ≥ 2 x tc(XTIM) NOTE: Restriction does not include external hardware wait states 3. Lead + Active: LR + AR ≥ 4 x tc(XTIM) LW + AW ≥ 4 x tc(XTIM) NOTE: Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions†: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 1 ≥ 2 0 ≥ 1 ≥ 2 0 0, 1 † No hardware to detect illegal XTIMING configurations or† XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1 † No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Asynchronous XREADY†: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Invalid 1 0 0 1 0 0 0, 1 Invalid 1 1 0 1 1 0 0 Valid 1 1 0 1 1 0 1 Valid 1 2 0 1 2 0 0, 1 Valid 2 1 0 2 1 0 0, 1 † No hardware to detect illegal XTIMING configurations |
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