CP3SP33SMSSLASHNOPB datasheet(206/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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22.10.12 CAN Interrupt Clear Register n (CICLRn)

The CICLRn register bits individually clear CAN interrupt pending flags caused by the message buffers

and from the Error Management Logic. Do not modify this register with instructions that access the

EICLR

ICLR

EICLR

The Error Interrupt Clear bit is used to clear the EIPND bit.

0 – The EIPND bit is unaffected by writing 0.

1 – The EIPND bit is cleared by writing 1.

ICLR

The Buffer Interrupt Clear bits are used to clear the IPND bits.

0 – The corresponding IPND bit is unaffected by writing 0.

0 – The corresponding IPND bit is cleared by writing 1.

22.10.13 CAN Interrupt Code Enable Register n (CICENn)

The CICENn register controls whether the interrupt pending flag in the CIPND register is translated into

the Interrupt Code field of the CSTPND register. All interrupt requests, CAN error, and message buffer

interrupts can be enabled/ disabled separately for the interrupt code indication field.

EICEN

ICEN

R/W

EICEN

The Error Interrupt Code Enable bit controls encoding for error interrupts.

0 – Error interrupt pending is not indicated in the interrupt code.

1 – Error interrupt pending is indicated in the interrupt code.

ICEN

The Buffer Interrupt Code Enable bits control encoding for message buffer interrupts.

0 – Message buffer interrupt pending is not indicated in the interrupt code.

1 – Message buffer interrupt pending is indicated in the interrupt code.

22.10.14 CAN Status Pending Register n (CSTPNDn)

The CSTPNDn register holds the status of the CAN Node and the Interrupt Code.

8 7

Reserved

IRQ

IST

The CAN Node Status field indicates the status of the CAN node as shown in Table 22-17.

Table 22-17. CAN Node Status

Node Status

000

Not Active

010

Error Active

011

Error Warning Level

10x

Error Passive

11x

Bus Off

206

Dual CAN Interfaces

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