PC87591L datasheet(271/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Debug ISE Source Registers A (DBGISESRCA)

DBGISESRCA is a word-wide read/write register that indicates the ISE sources. The register is cleared on reset. Writing 1

to a bit in this register clears it. Writing 0 to a bit does not change its value. The DBGISESRCA register format is shown

below.

Location: 00 FDEA16

Type: R/W S

4.19.10 Usage Hints

JTAG Performance

For best performance, the PC87591x should be the only device in the scan path. Since the Debugger interface is used in

the development phase of the product, this should not be a problem. Keep the scan path as short as possible.

JTAG Clock Rate

For reliable communication over the JTAG serial bus, the error probability should be extremely low. This can be achieved

by connecting the TAP to the JTAG bus controller card, paying attention to the TCK frequency, signal timing, this cable type

and cable length (for long cables, transceivers may be required).

Communication Lockout

Some erroneous operations by the host may cause a lockout of the communication hardware. Examples of such cases are:

●

Performing a data scan when the JTAG instruction is SCAN_RX with a PID value of ‘1111’

●

Performing a data scan with a JTAG instruction with a PID value that is not in the system (i.e., PID > 0)

●

Performing a SCAN_TX when the PID value is ‘1111’

A reset instruction is guaranteed to recover from all of these locked cases, but it resets the entire PC87591x.

Bit

Name

Reserved

Reset

00000000

Bit

76543210

Name

Reserved

ABORT_0

RX_0

Reset

00000000

Bit

Description

RX_i. The ISE source is the Rx data link. Turn on with ISE assertion. Turn off by writing a byte to DBGISESRC

containing 1 in the RX_i bit location.

0: Not an ISE source

1: The ISE source is the Rx data link

ABORT_i. The ISE source is an ABORT request by the debugger or one of the processors. This bit is set by

either an abort command from the debugger (SCAN_RX with PID=‘1111’) or by a write of a 1 to the processor’s

respective bit in DBGISECA register.

0: Not an ISE source

1: The ISE source is an ABORT event

7-2

Reserved. These bits are reserved for future expansion.

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