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PC87591L 데이터시트(PDF) 77 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC87591L
상세설명  LPC Mobile Embedded Controllers
PDF  437 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87591L 데이터시트(HTML) 77 Page - National Semiconductor (TI)

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4.0 Embedded Controller Modules (Continued)
Revision 1.07
77
www.national.com
When no Thold cycles are specified, SELn is deactivated in the clock cycle that follows T2, unless another read from the
same zone follows. The RD signal is always deactivated in the clock cycle following T2; see Figures 18, 19 and 20.
A burst bus cycle supplements the basic read bus cycle if the core attempts to access more bytes (i.e., a word) than the
configured bus width (and BRE in SZCFGn register is set to 1). The burst bus cycle (T2B) follows T2 before the Thold cycles
(if configured). A wait clock cycle (TBW) is added between T2 and T2B if WBR in SZCFGn register is set to 1.
The address of the burst bus cycle is changed on TBW (if configured) or T2B (if no TBW). At the end of T2B, data is sampled.
The RD signal is activated during the burst bus cycle and is deactivated in the clock cycle following T2B; see Figures 21 and
22.
CLK
A0-19
SELx
SELy
RD
WR0-1
D0-15
Normal Read
Normal Read
T1
T2
TIdle
T1
T2
In
In
(x
≠ y)
(y
≠ x)
BST0-2
Figure 18. Two Basic Normal Read Bus Cycles with Idle In Between (IPST Bit in SZCFGy Register = 1,
IPRE Bit in SZCFGx Register = 1)
Bus State
CLK
A0-19
SELn
D0-15
RD
WR0-1
Bus State
T1
TIW
TIW
T2
THold
BST0-2
Figure 19. Normal Read Bus Cycle with 2 Internal Waits and 1 Hold
In



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