PC87591L datasheet(93/437 Pages) NSC

93 / 437 page

Embedded Controller Modules (Continued)

Revision 1.07

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Device A Address Counter Register (ADCAn)

A double-word, read/write register. Holds the current address of either the source data item or the destination location, ac-

cording to DIR bit in DMACNTLn register. ADCAn is updated after each transfer cycle by INCAn, INCBn, ADA and ADB in

DMACNTLn register.

Location: Channel 0 - 00 FA0016

Channel 1 - 00 FA2016

Channel 2 - 00 FA4016

Channel 3 - 00 FA6016

Type: R/W

Device A Address Register (ADRAn)

A double-word, read/write register. Holds the starting address of either the next source data block, or the next destination data

area, according to DIR bit in DMACNTLn register.

Location: Channel 0 - 00 FA0416

Channel 1 - 00 FA2416

Channel 2 - 00 FA4416

Channel 3 - 00 FA6416

Type: R/W

Device B Address Counter Register (ADCBn)

A double-word, read/write register. Holds the current address of either the source data item, or the destination location, ac-

cording to DIR bit in DMACNTLn register. ADCBn is updated after each transfer cycle by INCAn, INCBn, ADA and ADB in

DMACNTLn register. In Direct (Fly-By) mode, this register is not used.

Location: Channel 0 - 00 FA0816

Channel 1 - 00 FA2816

Channel 2 - 00 FA4816

Channel 3 - 00 FA6816

Type: R/W

Device B Address Register (ADRBn)

A double-word, read/write register. Holds the starting address of either the next source data block or the next destination

data area, according to DIR bit in DMACNTLn register. In Direct (Fly-By) mode, this register is not used.

Location: Channel 0 - 00 FA0C16

Channel 1 - 00 FA2C16

Channel 2 - 00 FA4C16

Channel 3 - 00 FA6C16

Type: R/W

Bit

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Name

Device A Address Counter

Bit

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Name

Device A Address

Bit

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Name

Device B Address Counter

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

Name

Device B Address

PC87591L 데이터시트(PDF) 93 Page - National Semiconductor (TI)

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