PC87591L datasheet(87/437 Pages) NSC

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Embedded Controller Modules (Continued)

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4.2

DMA CONTROLLER (DMAC)

The DMAC transfers blocks of data between memory and I/O devices along four independent channels, with minimal inter-

vention by the core. The source and destination addresses and the block size to be transferred may be defined for each of

the channels.

4.2.1

Features

●

Four Independent Direct Memory Access (DMA) channels.

●

Direct (ﬂy-by) and indirect (memory-to-memory) transfer types.

●

Single-buffer, double-buffer and auto initialize operation modes.

●

Fixed address (I/O device) or updated (memory device).

●

Address update (increment or decrement) independent of the number of transferred bytes.

●

Interrupt line for each channel.

●

Programmable bus policy for each channel: continuous or intermittent use of the bus.

●

Software DMA request for each channel.

●

Maximum throughput in direct (ﬂy-by) transfer:

— Intermittent:Every three clock cycles.

— Continuous:On internal core bus - every clock cycle.

— Otherwise:Every two clock cycles.

●

Maximum throughput in indirect (memory-to-memory) transfer:

— Intermittent:Every ﬁve clock cycles.

— Continuous:On internal core bus - every two clock cycles.

— Otherwise:Every four clock cycles.

4.2.2

Functional Description

When transferring blocks of data using the DMAC, the source and destination addresses, as well as the block size and type

of operation, are set up in advance by programing the appropriate control registers. Actual data transfers are handled by the

DMAC channel in response to DMA transfer requests. On receiving a DMA transfer request (DMRQn), if the channel is en-

abled, the DMAC performs the following operations:

1. Acquires control of the core bus according to the DMAC priority on the core bus.

2. Determines priority among the DMAC channels, one clock cycle before T1 of the DMAC transfer cycle. (T1 is the first

clock cycle of the bus cycle.) Priority among the DMAC channels is fixed in descending order, with Channel 0 receiving

the highest priority.

3. Executes data transfer bus cycle(s) according to the values stored in the control registers of the channel being serviced

and according to the accessed memory address. It acknowledges the request during the bus cycle that accesses the

requesting device.

4. If the transfer of a block is terminated, the DMAC does the following:

— Updates the termination ﬂags.

— Generates an interrupt if enabled.

— Goes to step 6.

5. If DMRQn is still active and the Bus Policy is “continuous”, returns to step 3.

6. Relinquishes the internal core bus.

Each DMAC channel can be programed for direct (fly-by) or indirect (memory-to-memory) data transfer. Once a DMAC

transfer cycle is in process, the next transfer request is sampled when the DMAC acknowledge is deactivated and subse-

quently, on the rising edge of each clock cycle.

The configuration of either address freeze or address update (increment or decrement) is independent of the number of

transferred bytes, transfer direction or number of bytes in each DMAC transfer cycle. All these can be configured for each

channel by programing the appropriate control registers.

Each DMAC channel has eight control registers. DMAC channels are described hereafter with the suffix “n”, where n repre-

sents the channel number in the register name (n = 0 to 3).

4.2.3

Channel Assignment in PC87591x

Table 15 shows the assignment of the DMA channels to different tasks in the PC87591x. If a channel is used for memory

block transfers, other resources must be disabled.

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