PC87591L datasheet(59/437 Pages) NSC

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2.0 Signal/Pin Description and Configuration (Continued)

Revision 1.07

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External Interrupts Conﬁguration Register (EICFG)

The EICFG register is a read/write, byte-wide register. It enables the use of some of the external interrupts. The EICFG bits

have impact only when the pin is configured to its GPIO function. EICFG is cleared (0016) on reset.

Note that some of the pins that have an external interrupt (not controlled by the EICFG register) have an alternate function

that is an input. When a pin’s alternate function is selected, its interrupt function is also enabled.

The format of EICFG is as follows:

Location: 00 FF0016

Type: R/W

2.4.3

GPIO with Echo Configuration

Some of GPIO pins may be paired to generate an input to output echoing with software masking. The input GPIO are input

ports (Px or Py) with a wake-up function. The output ports are a Px type enhanced with the echo mechanism, as described

in Section 4.5.2 on page 114. The input echoing is enabled only when the respective Echo Enable bit in IOEE1-2 registers

is set. The input port should be configured to enable the interrupt function.

EXMEM16 (16-bit-Wide Expansion Memory). Enables the use of the 16-bit-wide Expansion memory, when the

ENEMEM is set. The bus width indicated in this register should be the same as the bus width deﬁned in Zone

0 of the BIU (SEL0).

0: The External Memory to be eight bits wide

1: Enables the use of a 16-bit-wide External Memory

4-3

CLKOM (Clock Out Mode). Selects the mode of operation of the CLKOUT signal. This ﬁeld is in effect only

when this signal is set for output.

Bits

4 3

Description

0 0:

Reserved (default)

0 1:

CLK - a clock at the core frequency is driven out

1 0:

32.768 KHz clock output

1 1:

Reserved

6-4

Reserved.

GTMON (Go-to Target Monitor Set Flag). This bit is set to indicate that the code should jump to the beginning

of the Target Monitor (TMON). The reset routine of the application should check this bit and behave accordingly.

Once cleared, this bit can not be set by software.

Bit

76543210

Name

Reserved

EXWINT46

EXWINT45

Reset

00000000

Bit

Description

EXWINT45 (Enable EXWINT45).

0: EXWINT45 input is blocked (disabled) while not being read as a GPIO.

1: EXWINT45 input is open; this enables the detection of changes on the input to trigger interrupts.

EXWINT46 (Enable EXWINT46).

0: EXWINT46 input is blocked (disabled) while not being read as a GPIO.

1: EXWINT46 input is open; this enables the detection of changes on the input to trigger interrupts.

7-2

Reserved.

Bit

Description

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