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PC87591L 데이터시트(PDF) 90 Page - National Semiconductor (TI) |
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PC87591L 데이터시트(HTML) 90 Page - National Semiconductor (TI) |
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90 / 437 page ![]() Embedded Controller Modules (Continued) www.national.com 90 Revision 1.07 4.2.5 Bus Policy Intermittent Operation Mode Figure 30. DMAC Direct Bus Cycles in Intermittent Mode, DMRQ Asserted Constantly. When BPC bit in DMACNTLn is 0, channel n is in Intermittent mode. In this mode, the DMAC channel relinquishes the bus after each transaction, regardless of the state of its DMA request input. In this way, the DMAC gives the core (and other DMA channels) a chance to use the bus, even if a DMA device needs the bus for multiple transfers. Continuous Operation Mode Figure 31. DMAC Direct Bus Cycles in Continuous Mode - External Bus When BPC bit in DMACNTLn register is 1, channel n is in Continuous mode. In this mode, a DMAC channel uses the bus continuously, as long as its request is active and BLTCn > 0. This allows the channel to utilize the full bandwidth of the bus. The activity of this channel cannot be interrupted by any other internal bus master, including higher priority DMAC channels. It is the system designer’s responsibility to limit the duration of the DMA request to prevent bus starvation. CLK DMRQi ADDR DMACKi T1 T2 T1 T2 Tidle Bus State ADCA ADCA Tidle Core Cycle Address CLK DMRQi ADDR DMACKi T1 T2 T2 Tidle T1 Bus State ADCA T1 Core Cycle Address ADCA T2 |
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