PC87591L datasheet(321/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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The SMI may be output from the PC87591x using the dedicated SMI signal or by routing SMI to an interrupt request channel

via the device’s configuration registers.

The Wake-Up Event Routing Control register, MSHEIEn, which is controlled by the core, holds an enable bit for each of the

events, which allows selective routing of these events to the core wake-up interrupt (MSWCI) to the MIWU. The core event

is controlled using a separate set of status signals to prevent race conditions when clearing events.

The MSWCI interrupt is a level high interrupt that gathers requests from MSHESn, MSWCTL2 and MSWCTL3 registers.

Once an output event is asserted, it keeps its active state until all set status bits are cleared or masked. This interrupt signal

is connected to the MSWC wake-up input of the MIWU. This enables handling state change requests even in Idle mode.

The MSWC output for this input is connected to the core through the MIWU module, enabling a power state change on in-

terrupt.

Event i

Detection

WK_SMIENn.i

WK_IRQENn.i

WK_ENn.i

Wake-Up Event i

From Wake-Up

PWUREQ

SMI

IRQ

Event

Routing

Logic

WK_STSn.i

Extension Logic

To Peripheral Bus

MSHEIEn.i

MSWCI

to MIWU

MSHESn.i

Figure 105. Wake-Up Event Routing Scheme

Wake-Up

From Host

I/F Module

SMI

Module SMI

PWUREQ

IRQj Wake-Up

PWUREQ Wake-Up Module

Wake-Up

IRQi Wake-Up

Figure 106. SMI and PWUREQ Source Gathering Scheme

from IRQs

Routing

PM1SMI

PM2SMI

PC87591L 데이터시트(PDF) 321 Page - National Semiconductor (TI)

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