PC87591L datasheet(332/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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Revision 1.07

MSWC Host Event Status Register 0 (MSHES0)

This register holds information similar to that in WK_STS0 register. The same event that causes a WK_STS0 bit to be set

sets the respective bit in MSHES0 register. Clearing bits is done for each of the status registers separately. This register is

reset to 0016 on VCC power-up or Host Domain Software reset. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6

of this register behaves in a special way on set and clear, as described below.

Location: Offset 00 FCCE16

Type: R/W1C

Bit

76543210

Name

EICFGPSO EICFGPBM

EIACPIS5

EIACPIS4

EIACPIS3

EIACPIS2

EIACPIS1

EIRTCAL

Reset

00000000

Bit

Description

EIRTCAL (Enable Interrupt on RTC Alarm). Mask generation of interrupt to the core on setting of the RTC

Alarm bit in MSWCTL1 register.

0: Interrupt disabled (default)

1: Generate a level high interrupt when the RTC Alarm bit is set

5-1

EIACPIS5-1 (Enable Interrupt ACPI request for S5 through S1). Mask generation of interrupt to the core on

changes to ACPISi (i=5-1) bit in MSWCTL2 register. An interrupt enable for ACPIS0 is enabled when any of

these bits is set.

0: Interrupt disabled (default)

1: Generate a level high interrupt on any change to the ACPISi bit

EICFGPBM (Enable Interrupt SuperI/O Conﬁguration Register D Power Button Mode). Mask generation of

interrupt to the core on changes to CFGPBM bit in MSWCTL2 register.

0: Interrupt disabled (default)

1: Generate a level high interrupt on any change to the CFGPBM bit

EICFGPSO (Enable Interrupt SuperI/O Conﬁguration Register D Power Supply Off). Mask generation of

interrupt to the core on changes to CFGPSO bit in MSWCTL2 register.

0: Interrupt disabled (default)

1: Generate a level high interrupt on any change to the CFGPBM bit

Bit

76543210

Name

Module IRQ

Event

Status

Software

Event

Status

Reserved

RING

Event

Status

Reserved

RI2

Event

Status

RI1

Event

Status

Reset

00000000

Bit

Description

RI1 Event Status.

0: Event not detected (default)

1: Event detected

RI2 Event Status.

0: Event not detected (default)

1: Event detected

Reserved.

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