PC87591L datasheet(351/437 Pages) NSC

351 / 437 page

6.0 Host-Controlled Modules and Host Interface (Continued)

Revision 1.07

351

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Shared Memory Conﬁguration Register

This register is reset on host domain hardware reset to 0016 or 0916, depending on the value of the SHBM strap input.

Location: Index F416

Type: R/W

Shared Memory Base Address High Byte Register

This register describes the high byte for the user-defined memory zone mapped to the shared memory (decoded as bits 31

to 24 of the 32-bit address range, bits 15-0 are 0). This register is reset to 0016 on Host Domain Hardware reset.

Location: Index F516

Type: R/W

Bit

76543210

Name

BIOS FWH ID

BIOS FWH

Enable

User-

Defined

Memory

Space

Enable

BIOS

Extended

Space

Enable

BIOS LPC

Enable

Reset

0000

Strap

Bit

Description

BIOS LPC Enable. Enables the PC87591x to respond to LPC memory accesses to the BIOS-LPC space. The

reset value of this register is deﬁned by the SHBM conﬁguration inputs. The value of this bit is updated later,

based on the detected host BIOS scheme; see “Memory Range Programing” on page 350 for details.

0: Disabled (default when SHBM disable BIOS configuration)

1: Enabled (default when SHBM enable BIOS configuration)

BIOS Extended Space Enable. Expands the BIOS address space to which the PC87591x responds to include

the Extended BIOS address range.

0: Disabled (default)

1: Enabled

User-Defined Memory Space Enable. When set, enables the PC87591x to respond to LPC memory read and

write accesses in the user-deﬁned memory area range. The base address and size of the user-deﬁned range

are speciﬁed by the Shared Memory Base Address High and Low Byte registers and the Shared Memory Size

Conﬁguration register.

0: Disabled (default)

1: Enabled

BIOS FWH Enable. When set, enables PC87591x response to LPC-FWH transactions to the BIOS-FWH

space. The reset value of this register is deﬁned by the XCNF(2-0) conﬁguration inputs. The value of this bit is

later updated based on the detected host BIOS scheme; see “Memory Range Programing” on page 350 for

details.

0: Disabled (default when SHBM disable BIOS configuration)

1: Enabled (default when SHBM enable BIOS configuration)

7-4

BIOS FWH ID. These four bits correspond to the identiﬁcation nibble, which is part of a FWH transaction (see

Section 6.1.7 for details).

Bit

76543210

Name

User-Deﬁned Memory Zone Address High

Reset

00000000

Bit

Description

7-0

User-Deﬁned Memory Zone Address High. Deﬁnes the higher eight bits of the user-deﬁned memory block

base address. The base address should be aligned on the selected block size.

PC87591L 데이터시트(PDF) 351 Page - National Semiconductor (TI)

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