PC87591L datasheet(119/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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When the signal’s direction is set as output (1), a value of 0 is forced. When the direction is set for input (0), the signal is in

TRI-STATE and is not forced low.

4.5.6

GPIO Port Registers

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

GPIO Register Map

Port Alternate Function Registers (PxALT, PyALT and PzALT)

These registers control the use of each of the Px, Py and Pz pins, respectively, as GPIO ports or as alternate functions.

●

When cleared (0), each bit in PxALT, PyALT or PzALT enables the corresponding pin as a GPIO signal.

●

When set (1), each bit enables the corresponding pin as an alternate function.

These registers are cleared (0) on reset, except when otherwise noted in Appendix A on page 408.

Location: See Appendix A

Type: R/W

Mnemonic

Type

PxALT

Port Px Alternate Function

R/W

PyALT

Port Py Alternate Function

R/W

PzALT

Port Pz Alternate Function

R/W

PxDIR

Port Px Direction

R/W

PwDIR

Port Pw Direction

R/W

PxDOUT

Port Px Data Output

R/W

PzDOUT

Port Pz Data Output

R/W

PwDOUT

Port Pw Data Output

R/W

PxDIN

Port Px Data Input

PyDIN

Port Py Data Input

PwDIN

Port Pw Data Input

PxWPU

Px Weak Pull-Up

R/W

PyWPU

Py Weak Pull-Up

R/W

Bit

76543210

Name

Px Pins Alternate Function Enable

Reset

00000000

Bit

76543210

Name

Py Pins Alternate Function Enable

Reset

00000000

Bit

76543210

Name

Pz Pins Alternate Function Enable

Reset

00000000

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