MT9072AB datasheet(46/275 Pages) ZARLINK

46 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

5.1.1

T1 D4 Framing

For D4 links the S-bit position contains an alternating 101010... pattern inserted into every second S-bit. These bits

are intended for determination of frame boundaries, and they are referred to as Ft bits. A separate fixed pattern,

repeating every superframe, is interleaved with the Ft bits. This fixed pattern (001110) is used to delineate the 12

frame superframe. These bits are referred to as the Fs bits. In D4 frames # 6 and #12, the LSB of each channel

byte may be replaced with A bit (frame #6) and B bit (frame #12) signaling information. See Table 8.

5.1.2

T1 ESF Framing

For ESF links the 6 bit framing pattern 001011, inserted into every 4th S-bit position, is used to delineate both frame

and superframe boundaries. Frames #6, 12, 18 and 24 may contain the A, B, C and D signaling bits, respectively. A

4 kHz data link is embedded in the S-bit position, interleaved between the framing pattern sequence (FPS) and the

transmit CRC-6 remainder (from the calculation done on the previous superframe). See Table 9.

Frame #

Signaling

Table 8 - D4 Superframe Structure (T1)

Frame #

FPS

FDL

CRC

Signaling

2CB1

6CB2

Table 9 - ESF Superframe Structure (T1)

MT9072AB 데이터시트(PDF) 46 Page - Zarlink Semiconductor Inc