MT9072AB datasheet(61/275 Pages) ZARLINK

61 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

For the National Bit Buffer transmit registers DL access to be enabled the SA4SS to SA8SS(register Y08) are set to

00.

Similarly, the DL data received on the PCM30 link is output to the National Bit Buffer receive data registers (register

address YC0-YC4), corresponding to bit positions as shown in Table 18. However, the National Bit Buffer receive

data registers are always enabled, regardless of the above control bit settings(SA4SS to SA8SS). Received DL

Data should be read from the National Bit Buffer receive data registers immediately following the CALN status

indication (during basic frame 0) and before the start of basic frame 1.

In order to facilitate conformance to ETS 300 233, three maskable interrupts are available for change of state of Sa

bits in the receive National Bit Buffer. These include Eight Consecutive Sa6 Nibbles (Sa6N8), Sa6 Nibble Change

(Sa6N) and Sa Nibble Change (SaN). See the detailed descriptions for these status bits provided in the CAS,

National, CRC-4 Local and Timer Interrupt Status Register (address Y36).

7.2.3

E1 Data Link (DL) ST-BUS Access

When the ST-BUS Data Link (DL) access is enabled, the setting of the 8 ST-BUS DSTi data bits determine the Data

Link (DL) output on the PCM30 link corresponding to bit positions one to three and Sa4-8 over each Non-Frame

Alignment Signal (NFAS) frame. Data for DL transmission should be written to DSTi immediately following the

NFAS frame (during FAS frames) and before the start of the next NFAS frame.

The ST-BUS Data Link (DL) access is enabled if the Sa Source Select Bits (Sa4SS-SA8SS) are set to ’10’ in

(bit positions one to eight of timeslot zero, of odd CRC-4 frames 1, 3, 5, 7, 9, 11, 13, 15).

The DL data received on the PCM30 link is always output to ST-BUS DSTo timeslot 0 during NFAS frames,

regardless of the settings of SA4SS to SA8SS.

Addressable Bytes

NFAS Frames of a CRC-4 Multiframe

Transmit

Address

Receive

Address

F11

F13

F15

TN0

YB0

RN0

YC0

Sa4

TN1

YB1

RN1

YC1

Sa5

TN2

YB2

RN2

YC2

Sa6

TN3

YB3

RN3

YC3

Sa7

TN4

YB4

RN4

YC4

Sa8

Table 18 - MT9072 National Bit Buffers (E1)

MT9072AB 데이터시트(PDF) 61 Page - Zarlink Semiconductor Inc

MT9072AB 데이터시트(HTML) 61 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL