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MT9072AB 데이터시트(PDF) 29 Page - Zarlink Semiconductor Inc

부품명 MT9072AB
상세설명  Octal T1/E1/J1 Framer
PDF  275 Pages
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제조업체  ZARLINK [Zarlink Semiconductor Inc]
홈페이지  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB 데이터시트(HTML) 29 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
29
Zarlink Semiconductor Inc.
34
54
74
114
134
154
L2
R4
T6
M14
H16
C14
DSTi[1]
DSTi[2]
DSTi[3]
DSTi[5]
DSTi[6]
DSTi[7]
I
Data ST-BUS. In 2.048 Mbit/s ST-BUS mode and IMA mode this pin is
an input for the transmit side of the framer. This pin is not used in
8.192 Mbit/s ST-BUS mode. The DSTi data stream is clocked into the
framer by the clock input to pin CKi. Pins DSTi[0-7] are used by
Framers[0-7] respectively.
In T1 mode, this pin accepts a 2.048 Mbit/s ST-BUS stream. The first
24 ST-BUS channels contain the data to be transmitted on the PCM24
interface. See Table 1.
In T1 IMA mode, this pin accepts a 1.544 Mbit/s serial stream that
contains a framing bit followed by the 24 8-bit channels to be
transmitted on the PCM24 interface, see Table 3. The framing bit is
ignored and an internally generated framing bit is used. IMA mode is
selected by setting the IMA bit (Address Y00) to 1.
In E1 mode, this pin accepts a 2.048 Mbit/s ST-BUS stream that
contains the data to be transmitted on the PCM30 interface. See Table
4 and Table 6.
In E1 IMA mode, this pin accepts a 2.048 Mbit/s ST-BUS stream that
contains the data to be transmitted on the PCM30 interface. IMA mode
is selected by setting the IMA bit (Address Y00) to 1. See Table 4 and
Table 6.
15
95
G1
T13
DSTo[0]
DSTo[4]
O
Data ST-BUS. This pin is an output for the receive side of the framer.
In 2.048 Mbit/s ST-BUS mode and IMA mode it operates the same as
DSTo(1-3), it can also operate in 8.192 Mbit/s ST-BUS mode. IMA
mode is not available at 8.192 Mbit/s. The DSTo data stream is
clocked out of the framer by the clock input to pin CKi.
When operated in 8.192 Mbit/s ST-BUS mode this pin outputs a data
stream containing 128 8-bit channels accommodating four framers.
See Table 2 and Table 5. The frame boundary is indicated by the FPi
inputs. Pin DSTo[0] is used by Framers[0-3] and pin DSTo[4] is used
by Framers[4-7].
The 32 ST-BUS channels mapped to each framer are treated as
described for DSTi(1-3) operating at 2.048 Mbit/s.
Pin Description (continued)
Pin #
Name
Type
Description (see Notes 1 to 7)
LQFP
LBGA



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