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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MT9072AB 데이터시트(PDF) 85 Page - Zarlink Semiconductor Inc |
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MT9072AB 데이터시트(HTML) 85 Page - Zarlink Semiconductor Inc |
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85 / 275 page  MT9072 Data Sheet 85 Zarlink Semiconductor Inc. 12.3 E1 Loopbacks In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9072 has 7 loopback functions. Table 40 specifies the registers related to controlling the different loopbacks. a) Digital loopback (DG Loop) - DSTi to DSTo at the PCM30 side. Bit DLBK = 0 normal; DLBK = 1 activate. The control bits for digital, remote, ST-BUS and payload loopbacks are located at address Y05. The remote and local timeslot loopbacks are controlled through control bits of the Timeslot Control register located at addresses Y90-YAF. b) Payload loopback (PL Loop) - Payload loopback (DSTo to DSTi). Bit PLBK = 0 normal; PLBK = 1 activate. The payload loopback is effectively a physical connection of DSTo to DSTi within the MT9072. Y35 Receive Line and Timer Interrupt Status LLEI and LLDI are the interrupts for LLED and LLDD. Y45 Receive Line and Timer Interrupt Mask LLEIM and LLDIM are the masks for LLEI and LLDI. Register Address Register Description Y01 Test, Error and Loopback Control Register The bits DLBK,RLBK, SLBK and PLBK can be used for digital loopback, remote loopback, ST-BUS and loopback. Y02 Interrupt and IO control register RxDO and RxCO have to one for certain loopbacks to work. Y90 to YAF Timeslot Control Register Local and Remote Timeslot Control Register allows for Timeslot Loopbacks (RTSLand TTSL). 904 Framer Loopback Global Register Framer to Framer ST-BUS and Remote Loopbacks. Table 40 - Register Related to Setting Up Loopbacks (E1) Register Address Register Description Table 39 - Registers Related to In Band Loopbacks (T1) MT9072 Tx DSTi DSTo System PCM30 MT9072 Tx DSTi DSTo System PCM30 Rx |
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