MT9072AB datasheet(138/275 Pages) ZARLINK

138 / 275 page

MT9072

Data Sheet

138

Zarlink Semiconductor Inc.

17.1.6

Interrupt Status Registers (Y30 - Y3F) Bit Functions

Interrupt status register bit functions are shown in Tables 105 to 108.

17.1.7

Interrupt Mask Registers (Y40 - Y4F) Bit Functions

Tables 109 to 115 describe the bit functions of each of the Interrupt Mask Registers in the MT9072. Each register

is repeated for each of the 4 framers (not the Interrupt Vector Mask). Framer 0 is addressed with Y=0, Framer 1

with Y=1, Framer 2 with Y=2. and Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB)

A11 A10 A9 A8). In addition, a simultaneous write to all 8 Framers is possible by setting the A11 address to Y=8

(1000). A (0) or (1) in the “Name” column of these tables indicates the state of the data bits after a hard reset (the

RESET pin is toggled from zero to one), or a software reset (the RST bit in control register address YF1 is toggled

from one to zero) or a T1E0 write to the Global Control Register bit 15.

Bit

Name

Functional Description

15-9

not used.

8GAI

Go Ahead Interrupt. Indicates a go-ahead pattern (01111111) was detected by the

HDLC receiver. This bit is reset after a read of Y33 or Y23.

7EOPDI

End of Packet Data Interrupt.This bit is set when an end of packet (EOP) byte was

written into the RX FIFO by the HDLC receiver. This can be in the form of a flag, an abort

sequence or as an invalid packet. This bit is reset after a read of Y33 or Y23.

TEOPI

Transmit End of Packet Interrupt.This bit is set when the transmitter has finished

sending the closing flag of a packet or after a packet has been aborted. This bit is reset

after a read of Y33 or Y23.

5EOPRI

End of Packet Receive Fifo Interrupt.This bit is set when the byte about to be read

from the RX FIFO is the last byte of the packet. It is also set if the Rx FIFO is read and

there is no data in it.This bit is reset after a read of Y33 or Y23.

4TXFLI

Transmit FIFO Low Interrupt.This bit is set when the Tx FIFO is emptied below the 16

byte low threshold level.This bit is reset after a read of Y33 or Y23.

3FAI

Frame Abort: Transmit Interrupt. This bit (FA) is set when a frame abort is received

during packet reception. It must be received after a minimum number of bits have been

received (26) otherwise it is ignored. This bit is reset after a read of Y33 or Y23.

TXUNDERI Transmit Elastic Buffer Empty Interrupt. If high it Indicates that a read by the

transmitter was attempted on an empty Tx FIFO. This bit is reset after a read of Y33 or

Y23.

RXFFI

Receive FIFO is filled above Threshold Interrupt.This bit is set when the Rx FIFO is

filled above the 16 byte full threshold level. This bit is reset after a read of Y33 or Y23.

0RXOVFLI

Receive Fifo Overflow Interrupt This bit Indicates that the 32 byte RX FIFO overflowed

(i/.e. an attempt to write to a 32 byte full RX FIFO). The HDLC will always disable the

receiver once the receive overflow has been detected. The receiver will be re-enabled

upon detection of the next flag, but will overflow again unless the RX FIFO is read. This

bit is reset after a read of Y33 or Y23.

Table 104 - HDLC Interrupt Status Register(Y33) (T1)

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