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MT9072AB 데이터시트(PDF) 220 Page - Zarlink Semiconductor Inc |
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MT9072AB 데이터시트(HTML) 220 Page - Zarlink Semiconductor Inc |
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220 / 275 page ![]() MT9072 Data Sheet 220 Zarlink Semiconductor Inc. 9F6RM (0) Framer 6 Rx LineMask. This is the mask bit for the F6RVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 8F6SM (0) Framer 6 Sync and Overflow Mask. This is the mask bit for the F6SVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 7F5HM (0) Framer 5 HDLC Mask. This is the mask bit for the F5HVS status bit in the Interrupt Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 6F5EM (0) Framer 5 Elastic Mask. This is the mask bit for the F5EVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 5F5RM (0) Framer 5 Rx Line Mask. This is the mask bit for the F5RVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 4F5SM (0) Framer 5 Sync and Overflow Mask. This is the mask bit for the F5SVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 3F4HM (0) Framer 4 HDLC Mask. This is the mask bit for the F5HVS status bit in the Interrupt Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 2F4EM (0) Framer 4 Elastic Mask. This is the mask bit for the F4EVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 1F4RM (0) Framer 4 Rx Line Mask. This is the mask bit for the F4RVS status bit in the Interrupt Vector register(address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 0F4SM (0) Framer 4 Sync and Overflow Mask. This is the mask bit for the F4SVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. Bit Name Functional Description Table 197 - Interrupt Vector 2 Mask Register (R/W Address 903) (E1) |
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