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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MT9072AB 데이터시트(PDF) 227 Page - Zarlink Semiconductor Inc |
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MT9072AB 데이터시트(HTML) 227 Page - Zarlink Semiconductor Inc |
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227 / 275 page  MT9072 Data Sheet 227 Zarlink Semiconductor Inc. Figure 13 - 8 T1 Links with Asynchronous Data Link Signaling Notes: Framer 1-8, 1 of MT9072 LIU 1-8, 8 of Generic LIU PLL, 1 of MT9042 HDLC, 8 of MT8952 - Framer elastic buffer is used. - Data Link data passes through the elastic buffer. - TxDLC & RXDLC outputs an enable signal - LIU Transmit JA and PLL are bypassed. - The MT8952B is in External Timing mode. RPOS RNEG RCLK TPOS TNEG TCLK LIU 1/8 RT RR TT TR Transmit xfmr LINE 1 Receive xfmr PRI SEC F0o C2o C4o PLL From RCLK’s of LIU’s LINES 2 to 7 Framers 2 to 7 RxDL RxDLC TxDL TxDLC CKi FPi LIU’s 2 to 7 6 RPOS RNEG EXCLi TPOS TNEG TXCL RxDL RxDLC TxDL TxDLC CKi FPi Framer 1/8 CDSTi RxCEN CDSTo TxCEN CKi HDLC 1/16 6 CDSTi RxCEN CDSTo TxCEN CKi HDLC 3-15 odd CDSTi RxCEN CDSTo TxCEN CKi HDLC 2/16 CDSTi RxCEN CDSTo TxCEN CKi HDLC 4-16 even 6 6 RCLK 6 |
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