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MT9072AB 데이터시트(PDF) 255 Page - Zarlink Semiconductor Inc

부품명 MT9072AB
상세설명  Octal T1/E1/J1 Framer
PDF  275 Pages
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제조업체  ZARLINK [Zarlink Semiconductor Inc]
홈페이지  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB 데이터시트(HTML) 255 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
255
Zarlink Semiconductor Inc.
Figure 49 - Receive DataLink Timing Diagram
Figure 50 - Receive Basic Frame Pulse Pin Timing
AC Electrical Characteristics - Receive Basic Frame Pulse Pin Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Basic Frame Output Delay
tBD
100
ns
150 pF load on RxBF
AC Electrical Characteristics - PCM24 Transmit Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Transmit Delay
tTD
50
ns
150 pF load on TPOS and TNEG
2
Transmit Delay in RZ mode
tr
TD
200
ns
150 pF load on TPOS and TNEG
3
Transmit Invalid in RZ Mode
tr
DI
200
ns
150 pF load on TPOS and TNEG
MT9072
Outputs Data
tCD
VT
VT
RxDLC - Note 2
(Output)
RxDL
(Output)
EXCLi
RXDL
Timeslots
VT
RxDLC - Note 3
(Output)
Note 1 - RxDLC output applies for every second frame (RxBF) pulse (250 us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y06)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y06)
S bit
Timeslot 23 Bit 8
VT
tDDR
tED
VT
Timeslot23
Bit 8
S
Bit
VT
tBD
RxBF
(Output)
EXCLi
RXDL
Bit Cells



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