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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ML7396AB 데이터시트(PDF) 94 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB 데이터시트(HTML) 94 Page - LAPIS Semiconductor Co., Ltd. |
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94 / 140 page  FEDL7396A/B/E-07 ML7396A/B/E 94/140 ●TX mode (Packet mode, packet length ≤ 256byte) Packet mode can be selected by setting DIO_EN ([PLL_MON/DIO_SEL:B0 0x69(1)]) =0b0. In Packet mode, each TX data is written into a FIFO by [WR_TX_FIFO:B0 0x7E] register. After writing full TX data of a packet, issuing TX_ON command. Following PB (preamble), SFD data, TX data is transmitted to the air. When CRC is enabled, the CRC calcuration will be done automatically and CRC result is set to FCS field and transmitted to the air. After TX completion interrupt (INT[16]/[17] group3) occurs, the interrupt must be cleared. If the next TX packet is sent, the next TX packet data is written to a FIFO. If RX is expected after TX, RX_ON should be issued by [RF_STATUS:B0 0x6E] register. TX can be terminated by issuing TRX_OFF by [RF_STATUS:B0 0x6E] register. At every packet writing, FIFO0 and FIFO1 are switched automatically. (FIFO0 → FIFO1 → FIFO0) |
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