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ML7396AB 데이터시트(PDF) 43 Page - LAPIS Semiconductor Co., Ltd.

부품명 ML7396AB
상세설명  Sub GHz band short range wireless transceiver IC
PDF  140 Pages
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제조업체  LAPIS [LAPIS Semiconductor Co., Ltd.]
홈페이지  http://www.lapis-semi.com/
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ML7396AB 데이터시트(HTML) 43 Page - LAPIS Semiconductor Co., Ltd.

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Normal mode
Normal mode determines IDLE or BUSY. CCA (normal mode) will be executed when RX_ON is issued while CCA_EN
([CCA_CNTRL:B0 0x15(4)])=0b1, CCA_IDLE_EN ([CCA_CNTRL:B0 0x15(3)])=0b0 and CCA_LOOP_START
([CCA_CNTRL:B0 0x15(5)])=0b0 are set.
The judgement of CCA is determined by average ED value in [ED_RSLT:B0 0x16] and threshold value defined by
[CCA_LEVEL:B0 0x13] register. If average ED value exceeds CCA threshold value, it is determined as “BUSY”. And set
CCA_RSLT[1:0] ([CCA_CNTRL:B0 0x15(1-0)]) =0b01 is set. If ED value is smaller than CCA threshold, and maintains
IDLE detection period which is defined by IDLE_WAIT[9:0] of the [IDLE_WAIT_L:B0 0x17], [IDLE_WAIT_H:B0 0x18]
resisters, it is determined as “IDLE”. And CCA_RSLT[1:0] = 0b00 is set. For details operation of IDLE_WAIT[9:0], please
refer to “IDLE detection for long period”.
If “BUSY” or “IDLE” is determined, CCA_DONE [CCA_CNTRL:B0 0x15(2)] will become 0b1 and CCA completion
interrupt (INT[08] group2) is generated. CCA_EN bit will be cleared to 0b0 automatically.
When CCA completion interrupt is cleared, CCA_RSLT[1:0] are reset to 0b00. Therefore CCA_RSLT[1:0] need to be read
before clearing CCA completion interrupt.
If an ED value exceeds the value defined by [CCA_IGNORE_LEVEL:B0 0x12] register, and as long as a given ED value is
included in the averaging target of ED value calculation, IDLE judgment is not performed. In this case, if average ED value
exceeds CCA threshold value, it is determined as “BUSY” and CCA operation is terminated. However, if average ED value is
smaller than CCA threshold value, IDLE judgment is not determined. And CCA_RSLT[1:0] indicates 0b11. CCA operation
continues until “BUSY” is ditermined or the given ED value is out of the averaging target and “IDLE” is determined. For
detail operation of ED value exceeding [CCA_IGNORE_LEVEL:B0 0x12] register, please refer to "IDLE determination
exclusion under strong signal input".
Timing from CCA command issue to the CCA completion is calculated as the following formula.
[IDLE detection]
CCA execution time = (ED value average times + IDLE_WAIT setting) * A/D conversion time +
filter stabilization time (A/D conversion time* 2)
[BUSY detection]
CCA execution time = ED value average times * A/D conversion time+ filter stabilization time (A/D conversion time* 2)
[Note]
1. Above formula does not consider IDLE judgment exclusion based on [CCA_IGNORE_LEVEL:B0 0x12] register.
For details, please refer to "DLE determination exclusion under strong signal input ".
2. A/D conversion time can be selected by ADC_CLK_SET ([ADC_CLK_SET:B0 0x08(4)]).
ADC_CLK_SET=0b0: 17.8μs, 0b1: 16μs



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