| 전자부품 데이터시트 검색엔진 |
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ML7396AB 데이터시트(PDF) 15 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB 데이터시트(HTML) 15 Page - LAPIS Semiconductor Co., Ltd. |
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15 / 140 page ![]() FEDL7396A/B/E-07 ML7396A/B/E 15/140 ●SPI interface characteristics Item Symbol Condition Min Typ Max Unit SCLK clock frequency FSCLK 0.032 2 16 MHz SCEN input setup time TSSNSU 30 - - ns SCEN input hold time TSSNH 30 - - ns SCLK high pulse width TWSCKH 28 - - ns SCLK low pulse width TWSCKL 28 - - ns SDI input setup time TSDISU 5 - - ns SDI input hold time TSDIH 15 - - ns SCEN negate interval TSSNAI 60 - - ns SDO output delay time TSDO Load capacitance CL=20pF - - 22 ns [Note] All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%. SCE SCLK MSB IN BITS6-1 LSB IN TSSNH BITS6-1 TSDO MSB OUT TWSCKL TWSCKH TSDISU TSDIH FSCLK TSSNSU SDI LSB OUT SDO TSSNAI SCE |
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