CS8420 datasheet(13/80 Pages) CIRRUS

13 / 80 page

CS8420

DS245PP2

direct 256*Fsi clock input via the RMCK pin, in-

stead of the PLL.

Figure 9 shows audio data entering via the AES3

Receiver. The PLL locks onto the pre-ambles in the

incoming audio stream, and generates a 256*Fsi

clock. The rate converted data is then output via the

serial audio output port and via the AES3 transmit-

ter.

Figure 10 shows the same data flow as Figure 7.

The input clock is derived from an incoming AES3

data stream. The incoming data must be synchro-

nous to the AES3 data stream.

Figure 11 shows the same data flow as Figure 7.

The input data must be synchronous to OMCK.

The output data is clocked by the recovered PLL

clock from an AES3 input stream. This may be

used to implement a “house sync” architecture.

Figure 8 shows audio data entering via the AES3

receiver, passing through the sample rate converter,

and then exiting via the serial audio output port.

Synchronous audio data may then be input via the

serial audio input port and output via the AES3

transmitter.

Figure 13 is the same as Figure 12, but without the

sample rate converter. The whole data path is

clocked via the PLL generated recovered clock.

Figure 14 illustrates a standard AES3 receiver

function, with no rate conversion.

Figure 15 shows a standard AES3 transmitter func-

tion, with no rate conversion.

Figure 7. Serial Audio Input, using PLL, SRC enabled

Figure 8. Serial Audio Input, No PLL, SRC enabled

Serial

Audio

Input

AES3

Encoder

&Driver

Serial

Audio

Output

Sample

Rate

Converter

ILRCK

ISCLK

SDIN

OLRCK

OSCLK

SDOUT

TXP

TXN

PLL

RMCK

OMCK

TXD1-0:

SPD1-0:

SRCD:

OUTC:

INC:

RXD1-0:

Clock Source Control Bits

Data Flow Control Bits

Serial

Audio

Input

AES3

Encoder

&Driver

Serial

Audio

Output

Sample

Rate

Converter

ILRCK

ISCLK

SDIN

OLRCK

OSCLK

SDOUT

TXP

TXN

RMCK

OMCK

TXD1-0:

SPD1-0:

SRCD:

OUTC:

INC:

RXD1-0:

Clock Source Control Bits

Data Flow Control Bits

AES3

Encoder

&Driver

Serial

Audio

Output

Sample

Rate

Converter

OLRCK

OSCLK

SDOUT

TXP

TXN

PLL

RMCK

OMCK

TXD1-0:

SPD1-0:

SRCD:

OUTC:

INC:

RXD1-0:

Clock Source Control Bits

Data Flow Control Bits

AES3

Rx &

Decode

RXP

RXN

Serial

Audio

Input

AES3

Encoder

&Driver

Serial

Audio

Output

Sample

Rate

Converter

ILRCK

ISCLK

SDIN

OLRCK

OSCLK

SDOUT

TXP

TXN

PLL

RMCK OMCK

TXD1-0:

SPD1-0:

SRCD:

OUTC:

INC:

RXD1-0:

Clock Source Control Bits

Data Flow Control Bits

AES3

RXP

RXN

Figure 9. AES3 Input, SRC enabled

Figure 10. Serial Audio Input, AES3 Input Clock

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