CS8420 datasheet(37/80 Pages) CIRRUS

37 / 80 page

CS8420

DS245PP2

11.9

Interrupt Register 2 Status (8) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once

since the register was last read. A ”0” means the associated interrupt condition has NOT occurred

since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode

is set to level and the interrupt source is still true. Status bits that are masked off in the associated

mask register will always be “0” in this register. This register defaults to 00.

VFIFO

Varispeed FIFO overflow indicator. Occurs if the data buffer in the SRC overflows. This will oc-

cur if the input sample rate slows too fast.

REUNLOCK

Sample rate converter unlock indicator. This interrupt occurs if the SRC is still tracking a chang-

ing input or output sample rate.

DETU

D to E U-buffer transfer interrupt. The source of this bit is true during the D to E buffer transfer

in the U bit buffer management process (block mode only).

EFTU

E to F U-buffer transfer interrupt. The source of this bit is true during the E to F buffer transfer

in the U bit buffer management process (block mode only).

QCH

A new block of Q-subcode data is available for reading. The data must be completely read with-

in 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block.

UOVW

U-bit FIFO Overwrite. This interrupt occurs on an overwrite in the U-bit FIFO.

11.10 Interrupt 1 Register Mask (9)

The bits of this register serve as a mask for the Interrupt 1 Register. If a mask bit is set to 1, the error

is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If

a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the

INT pin or the status register. The bit positions align with the corresponding bits in Interrupt Register

1. This register defaults to 00.

11.11 Interrupt Register 1 Mode Registers MSB & LSB(10,11)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. This code

determines whether the INT pin is set active on the arrival of the interrupt condition, on the removal

of the interrupt condition, or on the continuing occurrence of the interrupt condition. These registers

default to 00.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

3210

VFIFO

REUNLOCK

DETU

EFTU

QCH

UOVW

3210

TSLIPM

OSLIPM

SREM

OVRGLM

OVRGRM

DETCM

EFTCM

RERRM

3210

TSLIP1

OSLIP1

SRE1

OVRGL1

OVRGR1

DETC1

EFTC1

RERR1

TSLIP0

OSLIP0

SRE0

OVRGL0

OVRGR0

DETC0

EFTC0

RERR0

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