CS8420 datasheet(4/80 Pages) CIRRUS

4 / 80 page

CS8420

DS245PP2

Figure 11. Serial Audio Input, SRC Output clocked by AES3 Recovered Clock........................... 14

Figure 12. AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out.................. 14

Figure 13. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, no SRC............. 14

Figure 14. AES3 Input to Serial Audio Output Only ...................................................................... 14

Figure 15. Input Serial Port to AES3 Transmitter .......................................................................... 14

Figure 16. Serial Audio Input Example Formats............................................................................ 17

Figure 17. Serial Audio Output Example Formats......................................................................... 18

Figure 18. Jitter Attenuation Characteristics of PLL with “slow” Filter Components...................... 20

Figure 19. Jitter Attenuation Characteristics of PLL with “medium” Filter Components ................ 20

Figure 20. Jitter Attenuation Characteristics of PLL with “fast” Filter Components ....................... 20

Figure 21. AES3 Receiver Timing for C & U pin output data ........................................................ 22

Figure 22. AES3 Transmitter Timing for C, U and V pin input data............................................... 24

Figure 23. Mono Mode Operation Compared to Normal Stereo Operation................................... 25

Figure 24. Control Port Timing in SPI Mode.................................................................................. 26

Figure 25. Control Port Timing in I2C Mode .................................................................................. 27

Figure 26. Hardware Mode 1 - Default Data Flow, AES3 Input..................................................... 50

Figure 27. Hardware Mode 2 - Default Data Flow, Serial Audio Input .......................................... 53

Figure 28. Hardware Mode 3 - Transceive Data Flow, with SRC.................................................. 56

Figure 29. Hardware Mode 4 - Transceive Data Flow, without SRC............................................. 60

Figure 30. Hardware Mode 5 - AES3 Receiver Only..................................................................... 64

Figure 31. Hardware Mode 6 - AES3 Transmitter Only................................................................. 67

Figure 32. Professional Output Circuit ..........................................................................................70

Figure 33. Consumer Output Circuit..............................................................................................70

Figure 34. TTL/CMOS Output Circuit ............................................................................................ 70

Figure 35. Professional Input Circuit ............................................................................................. 71

Figure 36. Transformerless Professional Input Circuit .................................................................. 71

Figure 37. Consumer Input Circuit ................................................................................................ 71

Figure 38. TTL/CMOS Input Circuit ...............................................................................................71

Figure 39. Channel Status Data Buffer Structure.......................................................................... 72

Figure 40. Channel Status Block Handling When Fso is Not Equal to Fsi .................................... 73

Figure 41. Flowchart for Reading the E Buffer .............................................................................. 73

Figure 42. Flowchart for Writing the E Buffer ................................................................................ 73

LIST OF TABLES

Table 1. PLL External Component Values .................................................................................... 21

Table 2. Summary of all Bits in the Control Register Map............................................................. 29

Table 3. Hardware Mode Definitions ............................................................................................. 49

Table 4. Serial Audio Output Formats Available in Hardware Mode ............................................. 49

Table 5. Serial Audio Input Formats Available in Hardware Mode ................................................ 49

Table 6. Hardware Mode 1 Start-up Options................................................................................. 50

Table 7. HW Mode 2A COPY/C and ORIG/U Pin Function .......................................................... 53

Table 8. HW Mode 2 Serial Audio Port Format Selection ............................................................. 53

Table 9. Hardware Mode 2 Start-up Options................................................................................. 53

Table 10. Hardware Mode 3 Start-up Options............................................................................... 57

Table 11. Hardware Mode 4 Start-up Options............................................................................... 61

Table 12. Hardware Mode 5 Start-up Options............................................................................... 64

Table 13. HW 6C COPY/C and ORIG pin function ....................................................................... 67

Table 14. HW 6 Serial Audio Port Format Selection ..................................................................... 67

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