CS8420 datasheet(53/80 Pages) CIRRUS

53 / 80 page

CS8420

DS245PP2

14.3

Hardware Mode 2 Description

(DEFAULT Data Flow, Serial Input)

Hardware Mode 2 data flow is shown in Figure 27.

Audio data is input via the serial audio input port,

and rate converted. The audio data at the new rate

is then output both via the serial audio output port

and via the AES3 transmitter.

The C, U and V bits in the AES3 output stream may

be set in 2 methods, selected by the CUVEN pin.

When CUVEN is low, mode 2A is selected, where

COPY/C, ORIG/U and EMPH/V pins allow select-

ed channel status data bits to be set. The COPY and

ORIG pins are used to set the pro bit, the copy bit

and the L bit, as shown in Table 7. In consumer

mode, the transmitted category code shall be

‘0101100’, which indicates sample rate converter.

The transmitted U and V bits are 0.

When the CUVEN pin is high, mode 2B is selected,

where COPY/C, ORIG/U and EMPH/V become

serial bit inputs for C, U and V data. This data is

clocked by both edges of OLRCK, and the channel

status block start is indicated or determined by

TCBL. Figure 22 shows the timing requirements.

Audio serial port data formats are selected as

shown in Tables 8, 4, and 5.

Start-up options are shown in Table 9, and allow

choice of the serial audio output port as a master or

slave and whether TCBL is an input or an output.

The serial audio input port is always a slave.

The following pages contain the detailed pin de-

scriptions for hardware mode 2.

COPY/C ORIG/U

Function

PRO=0, COPY=0, L=0

PRO=0, COPY=0, L=1

PRO=0, COPY=1, L=0

PRO=1

Table 7. HW Mode 2A COPY/C and ORIG/U Pin

Function

AES3

Encoder

&Tx

Serial

Audio

Output

Serial

Audio

Input

Sample

Rate

Converter

C & U bit Data Buffer

Clocked by

Output Clock

Clocked by

Input Derived Clock

ILRCK

ISCLK

OLRCK

OSCLK

SDOUT

TXP

TXN

RMCK

LOCK

COPY/C ORIG/U EMPH/V CUVEN TCBL

DFC0

DFC1

S/AES

VD+

H/S

Output

Clock

Source

OMCK

Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)

are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.

VD+

SDIN

SFMT1 SFMT0

Figure 27. Hardware Mode 2 - Default Data Flow, Serial Audio Input

SFMT1 SFMT0

Function

Serial Input & Output Format IF1&OF1

Serial Input & Output Format IF2&OF2

Serial Input & Output Format IF3&OF3

Serial Input & Output Format IF4&OF3

Table 8. HW Mode 2 Serial Audio Port Format Selection

SDOUT LOCK

Function

Serial Output Port is Slave

Serial Output Port is Master

TCBL is an input

TCBL is an output

Table 9. Hardware Mode 2 Start-up Options

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