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CS8420 데이터시트(PDF) 42 Page - Cirrus Logic

부품명 CS8420
상세설명  DIGITAL AUDIO SAMPLE RATE CONVERTER
PDF  80 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8420 데이터시트(HTML) 42 Page - Cirrus Logic

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CS8420
42
DS245PP2
11.18 User Data Buffer Control (19)
UD
User data pin (U) direction specifier
0 - The U pin is an input. The U data is latched in on both rising and falling edges of
OLRCK. This setting also chooses the U pin as the source for transmitted
U data (default).
1 - The U pin is an output. The received U data is clocked out on both rising and falling edges
of ILRCK. This setting also chooses the U data buffer as the source of transmitted
U data.
UBM1-0
Sets the operating mode of the AES3 U bit manager
00 - Transmit all zeros mode (default)
01 - Block mode
10 - Reserved
11 - IEC consumer mode 4
DETUI
D to E U-data buffer transfer inhibit bit (valid in block mode only).
0 - Allow U-data D to E buffer transfers (default)
1 - Inhibit U-data D to E buffer transfers
EFTUI
E to F U-data buffer transfer inhibit bit (valid in block mode only).
0 - Allow U-data E to F buffer transfers (default)
1 - Inhibit U-data E to F buffer transfer
11.19 Q-Channel Subcode Bytes 0 to 9 (20 - 29) (Read Only)
The following 10 registers contain the decoded Q-channel subcode data
7
6
5
4
3210
0
0
0
UD
UBM1
UBM0
DETUI
EFTUI
7
6
5
4
3210
ADDRESS
ADDRESS
ADDRESS
ADDRESS
CONTROL
CONTROL
CONTROL
CONTROL
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS SECOND
ABS SECOND
ABS SECOND
ABS SECOND
ABS SECOND
ABS SECOND
ABS SECOND
ABS SECOND
ABS FRAME
ABS FRAME
ABS FRAME
ABS FRAME
ABS FRAME
ABS FRAME
ABS FRAME
ABS FRAME



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