DSP56156ROM datasheet(37/76 Pages) MOTOROLA

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Bus Arbitration Timing — Master Mode

(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)

Figure 22 Bus Arbitration Timing — Master Mode — Bus Acquisition

Table 18 Master Mode

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

CLKO High to BR Output Assertion

CLKO High to BR Output Deassertion

4.7

BG Input Asserted/ Deasserted to CLKO

Low (Setup)

9.2

—6.5

—4.5

—

CLKO Low to BG Input Invalid (Hold)

0—0—

0—

BB Input Deasserted to CLKO Low (Setup)

9.2

—

6.5

—

4.5

—

CLKO Low to BB Input Deasserted (Hold)

—

CLKO High to BB Output Asserted

4.7

Three-state

CLKO

(Output)

(Input)

(I/O)

A0-A15

PS/DS

R/W

Bus Arbitration Timing — Master Mode

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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