DSP56156ROM datasheet(14/76 Pages) MOTOROLA

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DSP56156 Data Sheet

MOTOROLA

Pin Descriptions

the codec control register COCR. This

pin should be left floating when the co-

dec is not used.

SPKP (Speaker Plus)

— output. This pin is

the positive analog output from the on-

chip D/A converter. This pin should be

left floating when the codec is not used.

SPKM (Speaker Minus)

— output. This pin is

the negative analog output from the

on-chip D/A converter. This pin

should be left floating when the codec

is not used.

VREF (Voltage Reference)

— output. This

pin is the op-amp buffer output in the

reference voltage generator. It has a

value of (2

/5)VCCA. This pin should al-

ways be connected to the GNDA

through two capacitors, even when the

codec is not used.

VDIV (Voltage Division)

— output. This

output pin is also the output to the on-

chip op-amp buffer in the reference

voltage generator. It is connected to a

resistor divider network located within

the codec block which provides a volt-

age equal to (2

/5)VCCA. This pin should

be connected to the GND via a capacitor

when the codec is used and should be

left floating when the codec is not used.

Power, Ground, and Clock

VCC (Power) — Power pins

GND (Ground)

— Ground pins

VCCS (Synthesizer Power) — This pin sup-

plies a quiet power source to the Phase-

Locked Loop (PLL) to provide greater

frequency stability.

GNDS (Synthesizer Ground)

— This pin sup-

plies a quiet ground source to the PLL

to provide greater frequency stability.

VCCA (Analog Power) — This pin is the posi-

tive analog supply input. It should be con-

nected to VCC when the codec is not used.

GNDA (Analog Ground)

— This pin is the an-

alog ground return. It should be con-

nected to digital GND when the codec

is not used.

EXTAL (External Clock)

— input. This input

should be driven by an external clock or

by an external oscillator. After being

squared, the input frequency can be

used as the DSP core internal clock. In

that case, it is divided by two to produce

a four phase instruction cycle clock, the

minimum instruction time being two in-

put clock periods. This input frequency

is also used, after division, as input

clock for the on-chip codec and the on-

chip PLL.

CLKO (Clock Output)

— output. This pin

outputs a buffered clock signal. By pro-

gramming two bits (CS1-CS0) inside

the PLL Control Register (PLCR), the

user can select between outputting a

squared version of the signal applied to

EXTAL, a squared version of the signal

applied to EXTAL divided by 2, and a

delayed version of the DSP core master

clock. The clock frequency on this pin

can be disabled by setting the Clockout

Disable bit (CD; bit 7) of the Operating

Mode Register (OMR). When disabled,

the pin can be left floating.

SXFC (External Filter Capacitor)

— This pin

adds an external capacitor to the PLL

filter circuit. A low leakage capacitor

should be connected between and lo-

cated very close to SXFC and VCCS.

Power, Ground, and Clock

On-Chip Codec

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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