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DSP56156ROM 데이터시트(PDF) 20 Page - Motorola, Inc

부품명 DSP56156ROM
상세설명  16-bit Digital Signal Processor
PDF  76 Pages
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제조업체  MOTOROLA [Motorola, Inc]
홈페이지  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56156ROM 데이터시트(HTML) 20 Page - Motorola, Inc

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AC Electrical Characteristics and Timing
20
DSP56156 Data Sheet
MOTOROLA
AC Electrical Characteristics
(GND = 0 V dc)
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of
0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and
MODC. These five pins are tested using the input levels set forth in the DC Electrical Charac-
teristics
. AC timing specifications which are referenced to a device input signal are measured
in production with respect to the 50% point of the respective input signal’s transition. The
DSP56156 output levels are measured with the production test machine VOL and VOH refer-
ence levels set at 0.8 V and 2.0 V respectively.
Clock Operation Timing
The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in
Figure 6.
NOTES: 1. Rise and fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is less than or equal
to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should
meet the specified values in the 40 MHz column (4 ns maximum).
2. The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is less than or equal to 20 MHz.
If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that TH
and TL meet the specified values in the 40 MHz column (12 ns minimum).
3. T = ICYC / 4 is used in the electrical characteristics. The exact length of each T is affected by the duty
cycle of the external clock input.
4. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and
at VCC/2 when not AC coupled.
Table 11 Clock Operation Timing
Num
Characteristics
Sym
40 MHz
50 MHz
60 MHz
Unit
Min
Max
Min
Max
Min
Max
1
Frequency of Operation (EXTAL)
f
0
40
0
50
0
60
MHz
2
Instruction Cycle Time = 2TC
ICYC
50
×40×33
×
ns
3
Wait State Time = TC = 2T
—
25
×
20
×
16.6
×
ns
4
EXTAL Cycle Period
TC
25
×
20
×
16.6
×
ns
5
EXTAL Rise Time (See Note 1)
—
4
—
3
—
3
ns
6
EXTAL Fall Time (See Note 1)
—
4
—
3
—
3
ns
7
EXTAL Width High
48-52% duty cycle
(See Notes 2, 3, 4)
TH
12
×
9.6
×
8
×
ns
8
EXTAL Width Low
48%-52% duty cycle
(See Notes 2, 3, 4)
TL
12
×
9.6
×
8
×
ns
Clock Operation Timing
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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