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SPC564A80L7 데이터시트(PDF) 127 Page - STMicroelectronics

부품명 SPC564A80L7
상세설명  Up to 4 multiply and accumulate operations per cycle
PDF  157 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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SPC564A80L7 데이터시트(HTML) 127 Page - STMicroelectronics

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SPC564A74L7, SPC564A80B4, SPC564A80L7
Electrical characteristics
Doc ID 15399 Rev 9
127/157
3.17.7
eMIOS timing
3.17.8
DSPI timing
DSPI channel frequency support for the SPC564A80 MCU is shown in Table 47. Timing
specifications are in Table 48.
Table 46.
eMIOS timing(1)
#
Symbol
C
Characteristic
Min.
Value
Max.
Value
Unit
1tMIPW
CC
D
eMIOS Input Pulse Width
4
—
tCYC
2tMOPW
CC
D
eMIOS Output Pulse Width
1
—
tCYC
1.
eMIOS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF
with SRC = 0b00.
Table 47.
DSPI channel frequency support
System
Clock (MHz)
DSPI Use
Mode
Max. Usable
Frequency
(MHz)
Notes
150
LVDS
37.5
Use sysclock /4 divide ratio.
Non-LVDS
18.75
Use sysclock /8 divide ratio.
120
LVDS
40
Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI
configuration DBR=0b1 (double baud rate), BR=0b0000
(scaler value 2) and PBR=0b01 (prescaler value 3).
Non-LVDS
20
Use sysclock /6 divide ratio.
80
LVDS
40
Use sysclock /2 divide ratio.
Non-LVDS
20
Use sysclock /4 divide ratio.
Table 48.
DSPI timing(1),(2)
#
Symbol
C
Characteristic
Condition
Min.
Max.
Unit
1tSCK
CC
D
SCK Cycle Time(3),(4),(5)
24.4 ns
2.9 ms
—
2tCSC
CC
D
PCS to SCK Delay(6)
22(7)
—ns
3tASC
CC
D
After SCK Delay(8)
21(9)
—ns
4tSDC
CC
D
SCK Duty Cycle
(
½tSC)–2
(
½tSC)+2
ns
5tA
CC
D
Slave Access Time
(SS active to SOUT driven)
—25
ns
6tDIS
CC
D
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or
invalid)
—25
ns
7tPCSC
CC
D
PCSx to PCSS time
4(10)
—ns
8tPASC
CC
D
PCSS to PCSx time
5(11)
—ns



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