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SPC564A80L7 데이터시트(PDF) 129 Page - STMicroelectronics

부품명 SPC564A80L7
상세설명  Up to 4 multiply and accumulate operations per cycle
PDF  157 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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SPC564A80L7 데이터시트(HTML) 129 Page - STMicroelectronics

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SPC564A74L7, SPC564A80B4, SPC564A80L7
Electrical characteristics
Doc ID 15399 Rev 9
129/157
Figure 23.
DSPI classic SPI timing — master, CPHA = 0
3.
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two SPC564A80 devices communicating over a DSPI link.
4.
The actual minimum SCK cycle time is limited by pad performance.
5.
For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output,
maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.
6.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
7.
Timing met when pcssck = 3(01), and cssck =2 (0000).
8.
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
9.
Timing met when ASC = 2 (0000), and PASC = 3 (01).
10. Timing met when pcssck = 3.
11. Timing met when ASC = 3.
12. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
Data
Last Data
First Data
First Data
Data
Last Data
SIN
SOUT
PCSx
SCK Output
4
9
12
1
11
10
4
SCK Output
(CPOL=0)
(CPOL=1)
3
2
Note: Refer to Table 48 for the numbers.



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