ST10F296 datasheet(233/346 Pages) STMICROELECTRONICS

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ST10F296E

System reset

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20.7

Reset circuitry

The internal reset circuitry is described in Figure 91. The RSTIN pin provides an internal

pull-up resistor of 50 k

Ω to 250 kΩ (the minimum reset time must be calculated using the

lowest value).

The internal reset circuitry also provides a programmable (BDRSTEN bit of the SYSCON

timer reset, or software reset).

This bidirectional reset function is useful in applications where external devices require a

reset signal, but, it cannot be connected to the RSTOUT pin.

In this case, the external memory can run codes before the EINIT instruction is executed

(end of initialization). The RSTOUT pin is pulled high only when EINIT is executed.

The RPD pin provides an internal weak pull-down resistor which discharges an external

capacitor at a typical rate of 200 µA. If the PWDCFG bit of the SYSCON register is set, an

internal pull-up resistor is activated at the end of the reset sequence. This pull-up charges

any capacitor connected to the RPD pin.

The simplest way to reset the device is to insert a capacitor, C1, between the RSTIN pin and

VSS, and a second capacitor, C0, between the RPD pin and VSS, with a pull-up resistor, R0,

between the RPD pin and VDD. The RSTIN input provides an internal pull-up device

equalling a resistor of 50 k

Ω to 250 kΩ (the minimum reset time must be determined by the

lowest value). Selecting C1, produces a sufficient discharge time to permit the internal or

external oscillator, and/or the internal PLL, and the on-chip voltage regulator to stabilize.

To ensure correct power-up reset with controlled supply current consumption, in particular if

the clock signal requires a long period of time to stabilize, an asynchronous hardware reset

is required during power-up. Consequently, it is recommended to connect the external R0-

C0 circuit shown in Figure 88 to the RPD pin. On power-up, the logical low level on the RPD

pin, forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-

up, R0, then charges the capacitor, C0. Note that an internal pull-down device on the RPD

pin is turned on when the RSTIN pin is low, and causes the external capacitor, C0, to begin

discharging at a typical rate of 100-200 µA. With this mechanism, after power-up reset, short

low pulses applied on RSTIN produce synchronous hardware resets. If RSTIN is asserted

longer than the time needed for C0 to be discharged by the internal pull-down device, the

device is forced into an asynchronous reset. This mechanism ensures recovery from

catastrophic failures.

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