ST10F296 datasheet(234/346 Pages) STMICROELECTRONICS

234 / 346 page

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Product(s)

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System reset

ST10F296E

234/346

Figure 88.

Minimum external reset circuitry

The minimum reset circuit of Figure 88 is not adequate when the RSTIN pin is driven from

the ST10F296E itself during software or watchdog triggered resets. This is because

capacitor C1 keeps the voltage on the RSTIN pin above VIL after the end of the internal reset

sequence, thus triggering an asynchronous reset sequence.

Figure 89 shows an example of a reset circuit. The R1-C1 external circuit is used to

generate power-up or manual reset and the R0-C0 circuit on RPD is used for power-up reset

and to exit from power-down mode. Diode, D1, creates a wired-OR gate connection to the

reset pin and may be replaced by an open-collector Schmitt trigger buffer. Diode, D2,

provides a faster cycle time for repetitive power-on resets.

R2 is an optional pull-up for faster recovery and correct biasing of the TTL open collector

drivers.

Figure 89.

System reset circuit

RSTOUT

RPD

RSTIN

Hardware reset

VCC

For power-up reset (and interruptible power-down mode)

External hardware

ST10F296

RPD

RSTIN

VDD

External hardware

VDD

External

reset source

Open-drain inverter

VDD

ST10F296

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 데이터시트(PDF) 234 Page - STMicroelectronics

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