ST72344S2 datasheet(108/247 Pages) STMICROELECTRONICS

108 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

108/247

Doc ID 12321 Rev 6

11.3.6

Summary of timer modes

11.3.7

Each timer is associated with three control and status registers, and with six pairs of data

registers (16-bit values) related to the two input captures, the two output compares, the

counter and the alternate counter.

Control register 1 (CR1)

Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is

set.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even

if there is no successful comparison.

Table 49.

Timer modes

Modes

Available resources

Input Capture 1

Input Capture 2

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Yes

Output Compare (1 and/or 2)

Yes

One-pulse mode

Not recommended (1)

Partially (2)

PWM mode

Not recommended (3)

See note 4 in One-pulse mode.

See note 5 in One-pulse mode.

See note 4 in Pulse-width modulation mode.

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Read/Write

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