STM32L471RG datasheet(174/218 Pages) STMICROELECTRONICS

174 / 218 page

Electrical characteristics

STM32L471xx

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DocID027226 Rev 1

Figure 27. SPI timing diagram - slave mode and CPHA = 0

tv(SO)

Data output valid time

Slave mode 2.7 < VDD < 3.6 V

Voltage Range 1

-12.5

Slave mode 1.71 < VDD < 3.6 V

Voltage Range 1

-12.5

Slave mode 1.71 < VDD < 3.6 V

Voltage Range 2

-12.5

Slave mode 1.08 < VDDIO2 < 1.32 V(3)

-25

62.5

tv(MO)

Master mode

2.5

12.5

th(SO)

Data output hold time

Slave mode

Slave mode 1.08 < VDDIO2 < 1.32 V(3)

th(MO)

Master mode

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50 %.

3. SPI mapped on Port G.

Table 82. SPI characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

STM32L471RG 데이터시트(PDF) 174 Page - STMicroelectronics

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