STM32L471RG datasheet(177/218 Pages) STMICROELECTRONICS

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STM32L471xx

Electrical characteristics

199

Figure 30. Quad SPI timing diagram - SDR mode

Figure 31. Quad SPI timing diagram - DDR mode

Table 84. QUADSPI characteristics in DDR mode(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FCK

1/t(CK)

Quad SPI clock

frequency

1.71 < VDD < 3.6 V, CLOAD = 20 pF

Voltage Range 1

MHz

2 < VDD < 3.6 V, CLOAD = 20 pF

Voltage Range 1

1.71 < VDD < 3.6 V, CLOAD = 15 pF

Voltage Range 1

1.71 < VDD < 3.6 V CLOAD = 20 pF

Voltage Range 2

tw(CKH)

Quad SPI clock high

and low time

fAHBCLK = 48 MHz, presc=0

t(CK)/2-2

t(CK)/2

tw(CKL)

t(CK)/2

t(CK)/2+2

tsf(IN);tsr(IN)

Data input setup time

Voltage Range 1 and 2

3.5

thf(IN); thr(IN)

Data input hold time

6.5

tvf(OUT);tvr(OUT)

Data output valid time

Voltage Range 1

Voltage Range 2

thf(OUT); thr(OUT)

Data output hold time

Voltage Range 1

Voltage Range 2

1. Guaranteed by characterization results.

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