ACEX1 datasheet(38/86 Pages) ETC

38 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Tables 11 and 12 summarize the ClockLock and ClockBoost parameters

for -1 and -2 speed-grade devices, respectively.

Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Input rise time

Input fall time

5ns

tINDUTY

Input duty cycle

fCLK1

Input clock frequency (ClockBoost clock

multiplication factor equals 1)

180

MHz

fCLK2

Input clock frequency (ClockBoost clock

multiplication factor equals 2)

MHz

fCLKDEV

Input deviation from user specification in the

Altera software (1)

25,000

(2)

PPM

tINCLKSTB Input clock stability (measured between

adjacent clocks)

100

tLOCK

Time required for ClockLock or ClockBoost

to acquire lock (3)

µs

tJITTER

Jitter on ClockLock or ClockBoost-

generated clock (4)

tINCLKSTB <100

250 (4)

tINCLKSTB < 50

200 (4)

tOUTDUTY Duty cycle for ClockLock or ClockBoost-

generated clock

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