ACEX1 datasheet(16/86 Pages) ETC

16 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 8. ACEX 1K Logic Element

The programmable flipflop in the LE can be configured for D, T, JK, or SR

operation. The clock, clear, and preset control signals on the flipflop can

be driven by global signals, general-purpose I/O pins, or any internal

logic. For combinatorial functions, the flipflop is bypassed and the LUT’s

output drives the LE’s output.

The LE has two outputs that drive the interconnect: one drives the local

interconnect, and the other drives either the row or column FastTrack

Interconnect routing structure. The two outputs can be controlled

independently. For example, the LUT can drive one output while the

improve LE utilization because the register and the LUT can be used for

unrelated functions.

The ACEX 1K architecture provides two types of dedicated high-speed

data paths that connect adjacent LEs without using local interconnect

paths: carry chains and cascade chains. The carry chain supports high-

speed counters and adders, and the cascade chain implements wide-input

functions with minimum delay. Carry and cascade chains connect all LEs

in a LAB and all LABs in the same row. Intensive use of carry and cascade

chains can reduce routing flexibility. Therefore, the use of these chains

should be limited to speed-critical portions of a design.

To LAB Local

Interconnect

Carry-In

Clock

Select

Carry-Out

Look-Up

Table

(LUT)

Clear/

Preset

Logic

Carry

Chain

Cascade

Chain

Cascade-In

Cascade-Out

To FastTrack

Interconnect

Programmable

PRN

CLRN

ENA

data1

data2

data3

data4

labctrl1

labctrl2

labctrl4

labctrl3

Chip-Wide

Reset

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