ACEX1 datasheet(15/86 Pages) ETC

15 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Each LAB provides four control signals with programmable inversion

that can be used in all eight LEs. Two of these signals can be used as

clocks, the other two can be used for clear/preset control. The LAB clocks

can be driven by the dedicated clock input pins, global signals, I/O

signals, or internal signals via the LAB local interconnect. The LAB preset

and clear control signals can be driven by the global signals, I/O signals,

or internal signals via the LAB local interconnect. The global control

signals are typically used for global clock, clear, or preset signals because

they provide asynchronous control with very low skew across the device.

If logic is required on a control signal, it can be generated in one or more

LEs in any LAB and driven into the local interconnect of the target LAB.

In addition, the global control signals can be generated from LE outputs.

Logic Element

The LE, the smallest unit of logic in the ACEX 1K architecture, has a

compact size that provides efficient logic utilization. Each LE contains a

4-input LUT, which is a function generator that can quickly compute any

function of four variables. In addition, each LE contains a programmable

flipflop with a synchronous clock enable, a carry chain, and a cascade

chain. Each LE drives both the local and the FastTrack Interconnect

routing structure. Figure 8 shows the ACEX 1K LE.

ACEX1 데이터시트(PDF) 15 Page - List of Unclassifed Manufacturers